1. Field of the Invention
This invention relates generally to a method and apparatus for detecting the occurrence of clock errors in digital computing systems, and, more particularly, to such a system in which arithmetic operations are carried out simultaneously in two identical hardware modules, the results are compared and complementary residue codes are used to detect missing clock phases in a multiple phase clock system.
2. Discussion of the Background
Error detection for clock signals can be one of the most difficult errors to trouble-shoot because errors can manifest themselves in many ways. In a system with extensive logic dedicated to capturing sufficient information to permit a First Time Occurrence (FTO) software analysis, the possibility of a clock error is especially troublesome because a clock error could mean the captured data may not be believed. The present invention provides for the detection of failing clock signals, and a measure of confidence that a clock signal error has not corrupted captured data.
The detection of clock signal errors is especially troublesome in an environment where a software analysis is used to automatically interpret the captured data, because clock errors can greatly distort the values which are captured. Failure of a clock phase can result in not gating functional registers, or the compare and capture registers themselves. Without the ability to detect whether or not these clock signals have failed, the driver modules for these signals would always have to be considered as possible sources of failure, which can lead to needless swapping of the modules in an attempt to fix the problem. Detection of clock errors is highly desirable, both for the case when the signals fail because the fault is immediately identified as a clock signal fault, and for the case when they do not, because the absence of a clock error detection eliminates the driver modules from consideration. This adds to the credibility of the values captured in the compare and capture registers.